Conventionally, in the design of communications system there is a trade off between bit error rate (BER) and transmission bit rate. Higher bit rates tend to have higher BERs. A well-known limit on capacity of a communications channel is known as the Shannon Limit. In practice, where forward error correction (FEC) is used, the Shannon Limit is a theoretical boundary on channel capacity for a given modulation and code rate, where the code rate is the ratio of data bits to total bits transmitted for some amount of time, such as a second. FEC coding adds redundancy to a message by encoding such a message prior to transmission.
Error correction codes, including one or more used in FEC, classically exist as block codes (Hamming, Bose-Chaudhuri-Hochquenghem (BCH), and Reed-Solomon), convolutional codes (Viterbi), trellis codes, concatenated (Viterbi/Reed-Solomon), turbo convolutional codes (TCCs), and turbo product codes (TPCs). With respect to TPCs, an extended Hamming code (a Hamming code with a parity bit) and parity codes are commonly used to construct product codes.
Others have suggested serial concatenated TCC encoding, then interleaving output from that first TCC encoding followed by TCC encoding again the interleaved output. Others have suggested that such serial concatenated TCC encoding is not bandwidth efficient and exhibits an undesirable error floor phenomenon. However, with respect to TPCs, it should be understood that they are based on block codes and not convolutional codes.
FIG. 1 illustrates an exemplary turbo encoder block diagram including two constituent encoders, e.g., encoder 101 and encoder 102, and an interleaver 103. The first encoder 101 process message blocks coupled to input signal 110. The first encoder 101 provides two outputs coupled to signals 112 and 113 respectively. Signal 112 may provide systematic (S) output data stream, where signal 113 may provide parity (P) output data stream. The second encoder 102 is coupled to receive input from interleaver 103. As shown in FIG. 1, interleaver 103 is coupled to receive the message blocks of input signal 110 in one order and writes such message blocks into an information array in a different order. Interleaver 103 may be a helical interleaver or a pseudo-random interleaver, among other well known interleavers. For purposes of clarity, a helical interleaver 103 is described, though other known interleaving may be used. The second encoder 102 processes the interleaved version of the message blocks provided by interleaver 103. The encoder 102 provides two outputs coupled to signals 117 and 118 respectively. Signal 117 may provide interleaved systematic (Si) output data stream, where signal 118 may provide interleaved parity (Pi) output data stream. In general, the Si output may be discarded, for example to minimize interconnect issues, as it may be regenerated from the S output data stream.
For instance, a decoder coupled to receive outputs from the encoder module 100 may perform both forward error correction (alpha) and backwards error correction (beta) state calculations through the state trellis. The alpha and beta state calculations are generally iterative to improve error correction performance. Also, the error correction performance of a decoder is greatly improved if the decoder has knowledge of both the initial and final states of the encoders. In general, the initial state of the encoder is known, since the encoders are reset before each message block. In contrast, the final state of an encoder is not known by a recipient decoder.
Trellis termination is a technique to provide a known final state at the end of a message block. The trellis termination generally determines additions input bits that returns an encoder to its initial state, e.g., reset state. The additional bits provide additional systematic and parity bits which must be appended to the encoded message, e.g., output of circuit 100. The additional bits are referred to as tail bits or trellis termination bits, and generally, they are appended at the end of the encoded message data stream.
Therefore, an efficient decoder design to decode an encoded message data stream or blocks including tail bits is needed to meet throughput and performance requirements.